This blog post contains a collection of research papers, books, labs, conferences and additional resources that solve problems related to Advanced VLSI (Chip) Logic Design, Physical Design, Synthesis and Verification using Machine Learning and Deep Learning. Feel free to add a paper or an article related to this domain by commenting below so that I will include it here 😊
CAEML Research Topics
- Modular Machine Learning for Behavioral Modeling of Microelectronic Circuits and Systems
- Behavioral Model Development for High-Speed Links
- Design Rule Checking with Deep Networks
- Optimization of Power Delivery Networks for Maximizing Signal Integrity
- Intellectual Property Reuse Through Machine Learning
- Models to Enable System-level Electrostatic Discharge Analysis
- Applying Machine Learning to Back End IC Design
- Models to Enable System-level Electrostatic Discharge Analysis
- Causal Inference for Early Detection of Hardware Failure
- NL2PPA: Netlist‐to‐PPA Prediction Using Machine Learning
- Fast, Accurate PPA Model‐Extraction
- Design Space Exploration Using DNN
- High-Speed Bus Physical Design Analysis through Machine Learning
Reinforcement Learning
General
- Machine Learning Applications in Physical Design: Recent Results and Directions
- Accelerating chip design with machine learning: From pre-silicon to post-silicon
- METRICS 2.0: A Machine-Learning Based Optimization System for IC Design
- New Directions for Learning-Based IC Design Tools and Methodologies
- Machine learning-based VLSI cells shape function estimation
- Improved Physical Design and Signoff Methodologies for Better Integrated Circuit Design Quality
- Machine learning in physical design
- Machine learning and pattern matching in physical design
- The impact of AI technology on VLSI design
- Physical Design for Nanometer ICs
- Machine Learning Based Variation Modeling and Optimization for 3D ICs
Timing
- Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing Analysis
- SI for free: machine learning of interconnect coupling delay and transition effects
- LSTA: Learning-based static timing analysis for high-dimensional correlated on-chip variations
- A Deep Learning Methodology to Proliferate Golden Signoff Timing
- Learning-Based Approximation of Interconnect Delay and Slew in Signoff Timing Tools
- Accelerated Path-Based Timing Analysis with MapReduce
- SLoT: A Supervised Learning Model to Predict Dynamic Timing Errors of Functional Units
- Machine Learning: Confluence with Timing/EDA
Macro Placement
- Machine Learning based Datapath Extraction
- Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model
- A Machine Learning Framework for Register Placement Optimization in Digital Circuit Design
- A Study of Floorplanning Challenges and Analysis of macro placement approaches in Physical Aware Synthesis
- A Genetic Algorithm for Macro Cell Placement
- Routability-Driven Blockage-Aware Macro Placement
- Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome
Placement
- DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement - [Github]
- Progress and Challenges in VLSI Placement Research
- A learning-based methodology for routability prediction in placement
- Detailed routing violation prediction during placement using machine learning
- Design Rule Violation Hotspot Prediction Based on Neural Network Ensembles
Routing
- RouteNet: routability prediction for mixed-size designs using convolutional neural network
- Design Rule Violation Hotspot Prediction Based on Neural Network Ensembles
- RouteNet: Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network
- Training a Fully Convolutional Neural Network to Route Integrated Circuits
- Accurate Machine-Learning-Based On-Chip Router Modeling
- Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning
Power
- PRIMAL: Power Inference using Machine Learning
- Learning-Based Prediction of Embedded Memory Timing Failures During Initial Floorplan Design
- Machine learning based generic violation waiver system with application on electromigration sign-off
- IR drop prediction of ECO-revised circuits using machine learning
- Machine-learning-based dynamic IR drop prediction for ECO
- Modelling and Simulation of the IR-Drop phenomenon in integrated circuits
- PSN-aware circuit test timing prediction using machine learning
Hardware Implementation
- VLSI Extreme Learning Machine: A Design Space Exploration
- VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing
- An Analog VLSI Deep Machine Learning Implementation
- Efficient Methods and Hardware for Deep Learning
- Deep Gradient Compression: Reducing the Compression Bandwidth for Distributed Training
- Energy efficient VLSI circuits for machine learning on-chip
FPGA
Labs
Resources
If you wish to learn how to build a chip, I have collected these resources for you!
In case if you found something useful to add to this article or you found a bug in the code or would like to improve some points mentioned, feel free to write it down in the comments. Hope you found something useful here.